eSiGe has been widely used for source/drain regions of P-type metal oxide semiconductor (PMOS) devices to improve mobility. Source/drain regions of eSiGe are typically formed in a sigma shape, although other shapes are possible as well. For convenience, the sigma shape will be referenced throughout the disclosure, but it should be understood that other shapes are included as well. For example, as illustrated in FIG. 1, for a PMOS gate electrode 101 with gate dielectric 103, nitride cap 105, and spacers 107, eSiGe source/drain regions 109 surrounded by the silicon substrate 111 have a sigma shape, which allows for a solid contact area 113 between contact 115 and the source/drain region 109. As illustrated in FIG. 2, dummy electrodes are often formed, for example, between cells to maintain a constant pitch between gate electrodes. Dummy electrodes 201 are generally formed on STI regions 203, which are formed of silicon oxide. SiGe cannot grow on silicon oxide materials. Consequently, as illustrated in FIG. 2, eSiGe source/drain region 205 for electrode 101 adjacent the dummy electrode and therefore abutting the STI has a “ski slope” shape 207 rather than the sigma shape for other PMOS source/drain regions which only contact silicon. The ski slope introduces large amounts of variation including strain loss, STI loss, and small areas, leading to reduced performance for different devices such as length of diffusion (LOD) devices (in which only a single polysilicon line is formed over the silicon area).
A need therefore exists for methodology enabling formation of uniform source/drain regions with a sigma shape including adjacent an STI boundary, and the resulting device.